Design of High-speed Floating-point Arithmetic on FPGAs
Jie Shao · Informatization Research · 2009
For optimizing floating-point units,a design based on pipeline techniques is described in this paper.For design of the floating-point adder,an improved dual-path architecture is used to reduce the latency of critical path.The reduction is due to a modified shifter unit and a Leading One Predictor(LOP) unit.By using a structure of 4-2 column compression tree with the Radix-4 Booth encoding and a modified 4-2 compression algorithm,the logical function of floating point multiplier is simplified and the throughput of the system is increased.The simulation results show that floating-point adder achieves 405 MHz and the floating-point multiplier achieves 429 MHz on Xilinx Virtex-4 series FPGA.