Design of a 32-Bit Floating-Point Array Multiplier and a Comparison of Algorithms
Zhi Fu · 2003
Algorithms for two's complement multiplication are discussed It has been found that Modified Booth Algorithm is an ideal algorithm, which can accomplish multiplication without considering signs of multiplier and multiplicand, eliminating the need for modifying the product, so that the operation speed of the multiplier is greatly improved The algorithm has been implemented in a 32bit floatingpoint array multiplier, which performs singlecycle multiplications on 24bit integer or 32bit floatingpoint values The multiplier is suitable for VLSI implementation and has been used in DSP chip design