Reconfiguration algorithm of low-power reconfigurable cache
Shiliang Tu · Jisuanji gongcheng yu sheji · 2006
With the advances in semiconductor technology,there is an impact on chip design that the power management has become a design constraint due to increase in power density.Because on-chip cache is one of the main sources of CPU,low-power cache architecture can effectively reduce the power consumption of CPU.The design of low-power cache is researched.The approaches frequently used in low-power cache design,the architecture of a low-power re-configurable data cache and the corresponding re-configuration algorithm are introduced.A new algorithm— low-high boundary(LHB) algorithm for reconfiguration is given.The experimental result show that LHB algorithm is better than the original algorithm in both performance and power consumption.