Design of High-speed FIR Filter Based on FPGA
Jiang Zhu · Informatization Research · 2009
To realize filtering of high-speed input data,and aiming at the design method of systolic FIR digital filter,this paper proposes a design method of high-speed FIR filter based on FPGA.The implementation of this design is illustrated by the process of designing a 16-tap FIR digital filter using VHDL language.Simulation by Modelsim shows that the design is feasible and can support high-speed data of 1 GSPS.