Optimized Design Research of Instruction Memory for Stream Architecture
Nan Wu · 2012
The huge VLIW code size has brought serious problems to the capacity and energy consumption of instruction memory in stream architecture.Through analyzing the characteristics of instruction,this paper proposes a novel domain-divided VLIW compression scheme,designs a distributed on-chip instruction memory for stream architecture and proposes a new SIMD pipeline execution model.The experiment results show that about 38% of the off-chip instruction accessing and 65% of the on-chip instruction memory space demand can be reduced by the compression;the distributed instruction memory depresses about 37% of the area of on-chip instruction memory,and about 8.92% of the area of MASA stream processor.At the same time,the energy consumption of the instruction memory is reduced by 61%.