Memory Mapping Algorithms in RTL Synthesis
Zhou Hai · 2001
A Register Transfer Level Mapping (RTLM) algorithm is presented in the paper, which is a library mapping technique for RT level components and supports the current design methodologies using high level design and design reuse The algorithm synthesizes the source memory using one or more memory modules from a target memory library Three sub problems for memory mapping are defined, i e port mapping, bit width mapping and word mapping Finally,these solutions are combined into an efficient memory mapping algorithm Experimental results show that RTLM is an effective approach for reuse of memory designs in high level synthesis