Design and Implementation of A Very-High Radix Floating-Point Division Unit
Jin Zhanpeng · Microelectronics & Computer · 2006
By utilizing industrial floating-point benchmarks, such as fpspec92, fpspec95, linpack, whetstone and flops, based on the concept of interlock distance, floating-point processing performance is analyzed. From the experimental results, it can be concluded that the performance will be better when the cycle delay of floating-point division is between 8 and 12 cycles. So, the cycle delay of the division unit implemented as a radix-256 divider in LongTeng microprocessor is designated to be 11 cycles. It is implemented in SMIC 0.18μm 1P5M CMOS technology. In the worst environment, it's speed reaches 233MHZ, as well as the area is 0.174 mm2.