Optimization Design of Digital Quadrature Demodulation Receiver Based on FPGA
Atr Lab · JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY · 2006
Under certain conditions, combining the polyphase filtering structure of decimation filter, put forward an optimum design method of quadrature demodulation receiver, which owns decimation structure. With the same number of multipliers in FPGA, the order of FIR filter in receiver with above optimum structure is nearly 4 times than it implemented in direct way. Finally the design instance is given.