Design of DDC Extractor based on Folded Structure
Xiang Gui Ling · Communications technology · 2011
To realize the Digital-Down-Convertor extractor,the employment of Cascaded-Integrator-Comb filter and the Half-Band filter with FPGA is an efficient way.However,the traditional design method seldom considers the limited area resources.This paper proposes a new design method based on folding technique,and this method could implement a time-multiplexed structure,and thus could save the function unit resources or the silicon area.The CIC and HB folding diagrams are derived with folding equation,and then coded with Verilog.Through the co-simulation of modelsim and matlab this design is successfully applied on Xilinx's xc4vfx20 FPGA.Synchronous clock design,with satisfaction in low latency and other performance requirements,is of prominent advantages of less area resources,lower power consumption,and higher stability.