Design of CMOS double-edge-triggered flip-flop
JI Hui-lian · Semiconductor Technology · 2003
In this paper,the logic constructions of a double-edge-triggered flip-flop and a single-edge-triggered flip-flop are analyzed on the basis of CMOS transmission gate.We introduce a set ofnovel double-edge-triggered flip-flop which can be implemented with fewer transistors than anyprevious design. Simulation using SPICE shows that this DET-FF has ideal logic functionality, asimpler structure,lower delay time and higher maximum data rate .The power dissipation in the DET-FF and traditional SET-FF is compared via consideration and simulations and it is shown that theproposed DET-FF reduces power dissipation by 61 while keep the same date rate.