Design of low power quad-edge-triggered flip-flop
Jizhong Shen · Journal of Circuits and Systems · 2012
A design of QETFF(quad-edge-triggered flip-flop) based on ternary clock is proposed according to the principle that power optimization of a circuit can be obtained through reductions of the clock frequency under the constraint that its original performance does exist and the design method of the binary DETFF(double-edge-triggered flip-flop) based on binary clock.Multivalued signals possess the large information-carrying capacity,which are applied in clock network in order to reduce the power dissipation of system.QETFF makes use of all the four edges of ternary clock with a simple structure,lowering power consumption for no redundant edges.HSPICE simulations show that the designed QETFF performs ideal logic functionality with low power that can serve in binary sequential circuits and also in multivalued sequential circuits.