A design-for-test for SRAM-based FPGA interconnect testing
Jiarong Tong · Journal of Circuits and Systems · 2008
The area of interconnection is largest in FPGAs.The interconnect is complicated and apt to be faulty.Many researchers do their best to reduce the time of testing in order to reduce the cost of testing.In this paper,we propose adding several shift register chains in FPGA chip to only configure the interconnect and the configuration time is reduced over 99%.This method can check or diagnose faults in FPGA.