Design of 43-bit Floating-Point Pipelined Multiplier
Sun Hai-jun · Dianzi qijian · 2006
A novel 43-bit floating-point pipelined multiplier IP chip-core is presented.This multiplier takes advantage of modified Booth3 algorithm to reduce the number of the partial products,and proposes an architecture of compressor combined compression array.By optimizing the 5-2 compressor,the 4-2 compressor and the 64-bit adder,this design can effectively reduce the propagation time and chip area.Being implemented on FPGA,our multiplier's operation performance is higher than that of the similar multiplier unit that the Altera Corporation recently provides by 15.4%.