A full-adder optimization design method in DSP
Jiangyi Shi · Journal of Circuits and Systems · 2006
Full adders are important components in the chip of digital signal processors (DSP), and each chip comprises many full adder cells. So it is an effective method to enhance the DSP performance by improving the adder style. In this paper, a novel CPL style full adder is proposed. We have done HSPICE simulation runs of the new style adder, 28-T CMOS full adder and conventional CPL style full adder. The result shows that the novel CPL adder consumes less power and has higher speed compared with the previous two full adders.