Design on FPGA Implementation of AES Algorithm Chip
Zibin Dai · Microelectronics & Computer · 2005
Algorithm for the Advanced Encryption Standard (AES) appears to be excellent in security, efficiency, and flexibility, so the importance of its hardware implementation is obvious. The advantage of using FPGA architecture to design a cryptographic chip is presented in the paper, which is based on the characteristics of algorithm for AES. The design of en/decryptographic module is described in detail. Software simulation is made by Quartus II. And synthesis re-sults are summarized.