Hierarchical routing architecture and partitioning approach for multiple FPGAs oriented to high performance computing
Xiao Chun-hu · Jisuanji yingyong yanjiu · 2015
To target the problems of performance,cost and energy consumption in large scale communications of high performance computing,this paper proposed a hierarchical routing architecture and partitioning approach for multiple FPGAs.This method compromised the merits of emerging high performance interconnects,and exploited the local and hierarchical properties of future large scale communications.The proposed approach could design the customized interconnect topology according to different applications to reduce the interconnect cost while keep the high performance.This approach can implement the fast mapping from the design to the real high performance computing system with multi-FPGAs,and accelerate the realization of high performance reconfigurable computing systems.