A High-speed and Low-power 16×16-bit Parallel Multiplier
Bing Shao · 2003
A highspeed and lowpower 16×16bit parallel multiplier in very large scale integration based on 06μm doublewell CMOS process is described in the paper In order to achieve lowpower operation, the multiplier was designed utilizing passtransistor logic circuits New circuit implementations for Modified Booth Encoder and 42 compressor circuitries have been proposed and simulated At a supply voltage of 25 V, multiplication time of the multiplier for the worst case is 718 ns and the average power dissipation is 945 mW at a frequency of 100 MHz