Hardwire Logic Implementation of a 8-point FFT Algorithm
Nanning Zheng · Microelectronics & Computer · 2002
A reasonable logic structure for a8-point FFT processor is described and the simulating result is given in my paper and we expatiate stressly the signed complex adder /subtracter concept.The architecture can compute one transform sample every4clock cycles in average.And the design has been implemented in the FLEX10K family of FPGAs.The throughput is up to2M transform samples per second,and such performance makes the design rather attractive for use in some applications,such as OFDM systems.