Optimized hardware design of CABAC binarizer and context modeler
Lu Yu · Journal of Circuits and Systems · 2013
This paper presents a hardware architecture of binarizer and context modeler which are two parts of the CABAC entropy encoder of H.264/AVC.A producer/consumer model is applied to CABAC encoder showing that the throughput of CABAC encoder is improved and the utilization ratio of hardware resources is raised by optimizing the distribution of the length of bin string produced by binarizer and context modeler.Based on the model analysis,a three-stage pipelined hardware architecture with syntax element(SE) merging and splitting strategies are proposed for the optimization of bin string length distribution.Simulation results show that our design processes 1.89 bins per cycle on average.It can work at 303 MHz with 22.26K gates targeting 0.13 μm CMOS process.