An Efficient Architecture for Fast Modular Multiplication in GF(2~m)
Zhang Min-xuan · Computer Engineering and Science · 2004
Speeding up the modular multiplication is the key to improving the performances of ECC algorithms in GF(2~m). After analyzing the point multiplication in EC,we educe the modular multiplication formula in GF(2~m) for the systolic implementation with partial-parallelism. We also design an efficient architecture of systolic arrays and study the performance of the array elements. Simulation results prove that the partial-parallel architecture can process modular multiplication efficiently with proper hardware cost.