Implementation of a Structure-Efficient Multiple-Input Floating-Point Adder on FPGAs
Yong Du · Computer Engineering and Science · 2006
A multiple-input floating-point adder is usually composed of several double-input floating-point adders,and it is inevitable to increase the logic resources and processing latency,which makes it harder and harder to meet the requirements of high-speed digital signal processing.This article puts forward a new floating-point format suitable for implementation on FPGAs and an efficient structure with which the adder can complete calculating within four clock cycles.Test data is presented at the end of this article.