Optimized Design of H.264 Deblocking Filter System Based on FPGA
Xueliang Du · Jisuanji gongcheng · 2008
This paper presents an optimized deblocking filter method.The design improves the speed of system and efficiency of bus via a pipeline with suitable stages,enhancing the parallelism,and using some local SRAM.The paper presents a hierarchy Finite State Machine(FSM) design method which can control the data path precisely and reduce the complexity of hardware.The Field Programmable Gate Array(FPGA) simulation displays that filtering one Macro Block(MB) only costs 220 cycles in the worst case.