Comparison between distributed arithmetic architectures of high-order digital filters
Yu Liu · Shengxue jishu · 2009
Based on FPGA a comparison between two distributed arithmetic algorithms(DA) of high-order FIR filters in function and architecture(LUT-based DA and Proposed DA) has been made.Proposed DA needs less memory and system resource than LUT-based DA due to a memory reduction technique.Recursive iteration of the memory reduction technique significantly increases the maximal number of filter order implementable on an FPGA platform by not only saving electronic devices,but also balancing hardware usage between logic element(LE) and memory.FPGA implementation results confirm that the proposed DA can implement a 1024-tap FIR filter with significantly smaller area usage than LUT-based DA.