Study of synthesis issues of Verilog language
Jianjun Jiang · Journal of Guangzhou University · 2006
Synthesis is the key tache for FPGA design because the hardware frame and performance of a system are dependent upon synthesis results.The present paper dealed with the effect of different code style on synthesis results in terms of RTL circuit models,and introduced the function of synthesis constraint model for famous DC synthesis tool,and provided the optimal synthesis design strategy for FPGA designer.