Design and Implementation of High-Speed Asynchronous FIFO
Min Zhou · Computer Engineering and Science · 2009
A high-speed asynchronous FIFO design and its ASIC implementation are introduced in this paper. This implementation uses a novel shift address coding instead of the traditional Gray code. This shift coding solves the meta-stable problem which usually happens in asynchronous circuits and shortens the critical path. It can run faster than the Gray code FIFO. The design uses the Verilog hardware description language, and has good portability and design flexibility. Finally, a synthesized timing result is given.