Software/Hardware Co-verification Based on SystemC and Verilog
Bai Na · Modern Electronics Technique · 2008
With respect to the verification bottleneck of current digital ASICs design and for the purpose of describing and verifying design object in a higher abstract level,a software/hardware co-verification method is presented,the method is based on processor core model of SystemC and others model of Verilog.The use of method in GIV processor's verification is illustra- ted and analyzed for detail.The experimental results reveal that with advantage of co-verification a verification of system function and structure design is implemented before manufacturing the chip to shorten research cycle,reduce manufacturing cost and improve verification reliability.