Design and Process of Distributed Multi-Cell Integrated Semiconductor Arrester
Rong Luo · 2012
A distributed multi-cell integrated semiconductor arrester was designed and fabricated.Based on traditional single-cell arrester with unchanged surface area and NPNPN five-layer structure in longitudinal profile,emitter area in the new structure was equally divided into 2(N+1) 2(N is 0,1,2,3,4) zones to constitute centrosymmetric multi-cell structure in base area,which optimized distribution of cathode emitter of the arrester,making surge current in the plane tend to be uniform throughout the chip and reducing heat concentration effect.It also increased current amplifying factor and reduced turn-on time of the arrester.The distributed multi-cell integrated semiconductor arrester using Ga diffusion and glass passivation solved problems of uneven heat,slow response and poor reliability in single-cell arresters.Test results showed that the new structure with improved anti-surge capacity was applicable for anti-lightning in communication systems.