A Low-Power-Oriented Mechanism for Shared Cache Partitioning on CMPs
Zhiheng Zhao · Computer Engineering and Science · 2010
As the development of CMPs,the size of a on-chip cache increases and it consumes more and more power of the whole system.How to reduce the power of cache has become a focus of many designers of modern caches.This paper investigates a low-power-oriented runtime mechanism for shared cache partitioning.A shared cache partitioning framework is proposed,and it uses the Miss Rate Monitors to collect the miss rate information of the current applications at run-time.Then the miss rates are inputted to a low-power-oriented cache partitioning model to get the partitioning solution within the performance degradation threshold(PDT).Our evaluation,on top of a two core CMP processor with a shared L2 cache,with 21 multi-program workloads,shows that when PDT is 1% and 3%,the rates of L2 cache shut-down will be up to nearly 20.8% and 36.9% respectively.