A JTAG Debugging Circuit with Pipeline Tracer for the 32-bit RISC CPU
Qianling Zhang · Microelectronics & Computer · 2004
A design of JTAG debugging circuit for the 32-bit RISC CPU is presented and a novel circuit architecture with the ability of branch predicting -pipeline tracer is depicted to solve breakpoint halt error by the multi-stage pipeline of the RISC CPU. The debugging circuit is compatible with the IEEE standard 1149.1. Its feature includes: Breakpoint, Single step, View or modify CPU register/memory space, in-circuit FLASH programming.