On the Implementation of a High-Throughput FPGA-Based Floating-Point FFT Processor
Xiao-Dong Yang · Computer Engineering and Science · 2008
In this paper,we design and implement a 32-bit IEEE 754 single precision floating-point FFT processor.Usually,limited by the long pipeline latency of floating-point operations and the number of the RAM ports on the FPGA chips the throughput of the traditional FFT processors can only reach approximately one result per cycle.Through making some improvements on the design of the butterfly unit architecture and reorganizing the RAM access,almost a throughput of 2 complex results per cycle can be obtained and twice performance over the traditional FFT processors can be achieved.As to a 1 024-point FFT transform,it can be finished in(512+10)10=5 220 cycles.