The application of FPGA in the digital channelized receiver
Yu Liu · Radar & Ecm · 2005
A design idea of the digital channelized receiver for electronic surveillance is introduced in this paper and the implementation structure of the FPGA is presented. The emphasis is put on the principle of adopting the polyphase filter and the FPGA to realize channelization. The simulation result in this regard is also given. In order to get to the effect of real-time processing, the structure of table look-up and the structrue of pipelining and parallelling are respectively employed in the FPGAs of FIR and FFT. These two ways greatly improve the operating rate and make the real-time processing of the digital channelized receiver possible. Besides,the frequency estimation and detection and the logic decision are introduced in the paper.