FPGA Implementation of Viterbi Decoding for Low-bit-rate Speech Communication
Pla Uni · Electronics Quality · 2009
Viterbi decoding is a maximum likelihood decode algorithm of the convolution code. A hardware implement architecture is proposed for the convolution coding and viterbi decoding using FPGA,and a channel-coding program based on(2,1,7) convolution code is used to protect the 2.4kbps MELP speech code parameters. Experiment result shows that this can efficiently improve the quality of speech parameters in noisy channel.