Design of MCML Structure High-speed and Low-power Adder
Ru Han · Microelectronics & Computer · 2004
This paper presents the design of MCML structure method. And a high-speed and low-power four-bit parallel adder is described. The layout is completed under the standard TSMC 0.25CMOS process, and with this process, its working frequency and the power dissipation are 1GHz and 1.5mW. This circuit can be used as adder cell in high-speed digital system.