A Distributed BIST control scheme for Complex
HE Rong-hui · Microelectronics & Computer · 2003
Low power design quests for low power testing scheme.This paper considers a BIST(built-in self-test)TPG(test pattern generator)which can reduce the power consumption during test without losing stuck-at fault coverage.By adding simple control logic on original LFSR(liner feedback shift regis-ter),both the clock and the outputs of LFSR are modified,and pseudo-SIC(single input change)test set is so gained,which highly reduces the average power consumption of CUT.Experi-mental results based on the ISCAS'85and89benchmark cir-cuits are reported,54.4%to98.0%of the original average power consumption is reduced,showing that this scheme is effective.