Implementation of a FIR Filter with FPGA
LU Dan-qian · Journal of Nantong University · 2007
This paper introduced how to design a FIR digital filter by using an add-tree function and the linear-phase architecture with FPGA.The implementation was simulated through the Verilog HDL in Quartus II.Compared with the traditional way of using shift-adder function and direct FIR model,this way is better.Especially when the orders of the filter increase,the advantage will be more obvious.