A VLSI architecture for low power hierarchical motion estimator
Zhu Guang-xi · Journal of China Institute of Communications · 2002
In this paper we propose a new low power hierarchical motion estimator VLSI architecture that supports the advanced prediction mode of recent low bit-rate video coders such as H.263 and MPEG-4. In the proposed VLSI architecture, a basic searching unit (BSU) is commonly utilized for all hierarchical levels to make a low power and small sized motion estimator. Also, since the proposed architecture provides a scheduled data flow, both a macroblock-based motion vector (MV) and four block-based MVs per macroblock can be simultaneously obtained for the advanced prediction mode. The result shown, the proposed motion estimator provides similar coding performance as that of the full search block matching algorithm (FSBMA), and can be widely used in low power video encoder forapplication of wireless communicate.