Implementation of Error Code Analyzer Based on NiosII
Xie Shijun · Informatization Research · 2009
Error code analyzer is used during development of communication products.In view of the special requirement to multi-channel test in satellite communications,an error code analyzer is designed based on FPGA and NiosⅡ processor under the SOPC builder.This paper introduces briefly basic operation principles of the analyzer,and its realization is described in detail.Three schemes: auto correlation,circular accumulation and self synchronizing are proposed to realize local code generator and their performances are compared.At last,some of software code based on NiosⅡ are presented.It is shown by practical application that there are several good characteristics such as quick synchronization,high reliability,low resource consumption and so on.