Design of FIR Filter Based on the Distributed Arithmetic
WU You-fu · Information and Electronic Engineering · 2007
The paper introduces the new scheme design of FIR filter based on FPGA.The hardware of the digital FIR filter is implemented with the distributed arithmetic,programmed with VHDL language.The experiment results indicate that the approach is feasible,and it can make the design easier.It not only saves the resource of hardware,but also raises the speed of digital signal processing by using adder as a substitute for multiplier.