Efficient Implementation for Hash Function SHA-512
YI Lu-nan · Jisuanji gongcheng · 2007
A novel FPGA implementation of the secure hash algorithm 512(SHA-512) is proposed.The proposed architecture exploits the benefits of parallel computer through pre-computation of intermediate temporal values.Parallel computer is based on the decomposition of the SHA-512 expression to separate information dependencies and independencies.This allows pre-computation of intermediate temporal values in parallel to the calculation of other independent values.The implementation's characteristics are compared to alternative implementations proposed by the academia and the industry,which are available in the international IP market.The proposed implementation achieves a throughput that exceeds 1 652Mbit/s,which is the highest among MD-5 and SHA-1 IP core for the targeted XILINX technology.