Verilog RTL Model
Li Shen · Journal of Tongji University · 2002
The VLSI testing is being pushed to the high-level based technology.The paper presents a Verilog RTL model(VRM) for integrated circuits.It provides a text format file that may be useful for developing RTL fault simulation and test pattern generation tools in practice.Based on the VRM,a simple RTL logic simulator was implemented for verification of the model.