Intrinsic Hardware Evolution Based on a Prototype of Function Level FPGA
Zhao Shu · Chinese Journal of Computers · 2002
Although evolvable hardware(EHW)promises to provide an entirely new approach to complex electronic circuit design and new adaptive hardware,most of EHW work concentrates on evolutionary design of electronic circuits,which is faced with a lot of problems.In order to loosen some bottlenecks restricting the speed and scale of evolutionary design,such as high computational cost and low speed of fitness evaluation,we present an intrinsic evolution technique with a detailed discussion.The technique mainly includes three parts:an efficient chromosome representation scheme using function transform,a relevant intrinsic evolution test bed comprising a prototype of function level field programmable gate array,and methods of online fitness evaluation and genetic parameter self adaption.On the basis of minimal term expression of logical functions,the new representation scheme can be expected to reduce the length of chromosome by a factor of n ,where n is the number of inputs.Based on a RAM look up table,the prototype of function level FPGA matches the representation scheme very well,and is suitable for implementation of various kinds of medium scale combinatorial and sequential logic functions.Designed as a PC extended card,the test bed supports partial reconfiguration of the prototype and online evaluation.Moreover,probabilities of crossover and mutation were allowed to adapt to changes in average fitness of population so as to quicken the convergence of evolution.The experimental results on some rather difficult but valuable design tasks,such as 4 bit extensible binary comparator and traffic light controller(a 4 state finite state machine),show us that much improvement is made in computational cost,evolution speed and evolvable scale of circuits.