An Efficient Architecture Design of Reconfigurable Float-point FFT Processor
Wei Gao · Microelectronics & Computer · 2012
Large resource cost is the design bottleneck of high-precision float-point FFT processor,a novel R2/22SDF reconfigurable architecture using shared-butterfly which employs single-port-based FIFO.Radix 2/22algorithm and pipeline architecture,which is suitable for float-point design,can reduce the multiplicative complexity and improve the multiplication efficiency.The FIFO memory using double-width single-port ram can avoid the larger area and power coat of dual-port ram.Two butterfly units can be merged by the proposed shared-butterfly architecture,which solves the low utilization factor problem of traditional single-path-delay-feedback architecture.The float-point design cost is efficiently reduced and the calculator utilization factor is improved,compared with the traditional pipeline method.