Hybrid Custom Hardware Acceleration for Coarse-grained Dataflow Network Processor
Zhigang Sun · Computer Engineering and Science · 2011
Aimed at the limitation of ILP exploitation and the fixed topology of control-flow NP, a novel scheme of coarse-grained dataflow NP architecture-DynaNP is presented in this paper. DynaNP not only improves the programmability of the NP by the control-flow structure of Processing Elements (PEs), but also effectively exploits the task-level parallelism by introducing a data-flow model into the packet processing. Moreover,to further improve the system throughput of DynaNP, a mechanism of hybrid custom hardware acceleration is proposed taking consideration of the multi-core and dataflow characteristics of DynaNP. Moreover, some key techniques of implementing the hybrid custom hardware accelerating unit are also addressed. The mechanism provides a unified interface for two kinds of hardware acceleration of custom instructions and coprocessors.