Software Decision Decoding of Fano Decoding Algorithm and the FPGA Implementation Method of Its Decoder
Jang Yuzhong · Informatization Research · 2009
Limited by the architecture of computer,the decoding speed of software implementation of Fano decoder is slow.To improve the decoding speed,we studied the hardware implementation of sequential decoder.An Field Programmable Gate Array(FPGA) prototype of the decoder is built,using Altera Hardware Description Language(AHDL).The state machine,the key part of Fano decoder,is described in detail in this paper.The result shows that the hardware implementation of sequential decoder has speed faster than that of the software implementation by at least 20 times with the same frequency.