Design and Implementation of the Floating-Point Pipelining in 32-bit RISC Microprocessor "LongTeng R2"
Min Luo · Microelectronics & Computer · 2006
This thesis proposes the architecture of the floating-point unit in a 32-bit RISC microprocessor LongTeng R2, and emphatically discusses the design and implementation of a high-performance floating-point pipelining with out-of-order execution and out-of-order termination. Aiming at the precise interruption response in floating-point pipelining, we utilize a precise interruption prediction method based on the exponents of operands and the types of operations, by whose predicted results the issue strategy can be determined. Through the simulation and synthesis based on the standard cells of 0.18μm technology, we can conclude that, compared with the floating-point unit with in-order control and Tomasulo Algorithm, this implementation achieves a satisfactory result with a smaller area as well as satisfies all the requirements and specifications of the microprocessor.