The Design and Simulation of Frequency Divider on CPLD/FPGA
Wang Jing · Journal of Lanzhou Jiaotong University · 2010
The basic and improved algorithms of decimal frequency are proposed on the basis of describing integer and half-integer frequency division algorithms,programming by Verilog HDL Language.The simulation test has been performed in Quartus Ⅱ,and the algorithm has been achieved on Altera's chips—EPM240T100I5.The test showes that the integer and half-integer frequency division can be achieved on the CPLD / FPGA,and the decimal frequency division can also be achieved on statistical average sense.