Design of DPLL Based on FPGA
Tao Yang · The Internet of Things · 2011
A DPLL based on FPGA by using verilog HDL language is introduced for analyzing the system perfor-mance and computer simulation. A comprehensive simulation tool Quartus Ⅱ 8.0. was used to perform input, functional and timing simulation and device programming for digital phase-locked loop. Simulation results show that the automatic variable module should be added to the traditional digital PLL to shorten the capture time and reduce the conflict among the synchronization error.