Monolithic Integrated 16×16 bit Multiplier Operating in Parallel and Pipeline
IC Design · 1992
The principle of 16× 16 bit multiplier operating in parallel and pipeline and controlled by two nonoverlapping pulses is described. With standard cells, the circuit was designed by CADand fabricated in 2μm CMOS process with double metallizations. The chip including more than7000 gates has an area of 8758 ×8878μm~2, The measured results show that it has expectedfunctins and can complete a multiplication Operation of 16×16 bit in a speed of 7MHz.