A High Throughput and Low-Power Implementation of the SHA-1 Hash Function
Zou Xue-cheng · Microelectronics & Computer · 2008
Secure hash algorithms are widely used in data integrity and digital signature authentication.A new hardware architecture was developed to speed up and reduce the power of the widely used secure hash algorithm SHA-1.The design performs two operations per cycle,hence 40 cycles to generate the hash value instead of 80 cycles.The optimized ASIC implementation improves the maximum throughput by 31% using 0.18μm CMOS technology,furthermore,it delivers a power dissipation reduction of 20%.