Bus Interface Protocol Testbench Based on Extended Finite State Machine and Assertion
Jing Gao · Journal of Tianjin University Science and Technology · 2008
In SoC design flow,traditional simulation and verification have limitations such as invisibility,uncontrollability and low automation.An SoC interface protocol testbench based on the extended finite state machine(EFSM)and assertion was proposed.It was a self-reactive testbench,which could not only automatically generate massive protocol-compliant stimulus,but improve the simulation automation by providing numerous biasing options based on feedback on assertion statistical information.A verification experiment to Wishbone bus interface protocol of video post-processing chip was performed with this testbench.Experimental results show that this testbench can shorten simulation time by 55%—65%,and effectively improve the verification quality and efficiency.